Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration bitstream may be read from an external memory, conventionally an external integrated circuit memory EEPROM, EPROM, PROM, and the like, though other types of memory may be used. The collective states of the individual memory cells then determine the function of the FPGA.
Dedicated logic circuits configured to perform specific functions are commonly embedded into PLDs. For example, the Virtex®-II family of FPGAs manufactured by Xilinx, Inc., include dedicated multipliers. Current approaches for embedding dedicated logic circuitry within a PLD are fundamentally limited in input/output (I/O) capacity by the routing and data-path processing capabilities of the programmable fabric to which the dedicated logic circuitry is attached. For example, a design in an FPGA may have a data path clocked at 300 MHz. A multiplier, attached to the data path of the FPGA, is also clocked at 300 MHz, even though a multiplier fabricated with the same process used for the FPGA is capable of being clocked at a higher rate.
Notably, conventional dedicated logic circuitry within an FPGA that operates using a higher or lower clock frequency than that of the FPGA fabric is clock asynchronously from the FPGA fabric. For example, embedded microprocessors, boundary scan circuitry, and I/O transceivers all operate asynchronously with respect to the FPGA fabric. Data transfer between the FPGA fabric and such dedicated logic circuits is effectuated using asynchronous communication between the FPGA fabric and the dedicated logic circuit (e.g., a first-in, first-out (FIFO) interface), or a handshaking mechanism (e.g., a processor bus and peripheral management).
Therefore, it would be desirable and useful to have an integrated circuit with embedded dedicated logic circuitry capable of operating at a higher clock rate and at least partially synchronous with programmatically configurable logic of such an integrated circuit.